1. Field of the Invention
This invention relates generally to semiconductor fabrication, and, more particularly, to an improved method for controlling the critical dimension of gate electrodes and the drive current in field-effect transistors.
2. Description of the Related Art
Methods for fabricating field-effect transistors, as well as their basic structures, are well known. The gate structure of such a transistor is fabricated by first forming a dielectric layer on the surface of a semiconducting substrate, followed by forming a gate conducting layer on the surface of the dielectric layer. Thereafter, the conducting layer and underlying dielectric layer are patterned by any one of a variety of suitable photolithographic and etching processes to form a transistor gate structure comprised of a gate electrode and gate dielectric. A plurality of source/drain regions are then formed in the substrate adjacent the sides of the gate structure. Typically, the source/drain regions are formed by an ion implantation process that introduces a p-type or n-type dopant material, for example, boron, phosphorus, arsenic, or the like, into the source/drain regions.
As transistor geometries continue to shrink, controlling the critical dimensions of gate structures can be difficult. FIG. 1 illustrates a polysilicon gate structure 19 produced according to a prior art fabrication process. The gate structure 19 is comprised of a polysilicon gate electrode 16 and an underlying gate dielectric 14 formed above the surface of a semiconducting substrate 10 in an active area defined by field oxide 12. After the polysilicon gate electrode 16 is formed, the sidewall surfaces 18 of the gate electrode 16 typically have a roughened, scallop-like appearance, as depicted in FIG. 2. Unfortunately, this roughness on the sidewalls 18 of the gate electrode 16 can adversely impact transistor performance characteristics, for example, by increasing transistor leakage current. Leakage current is believed to result from a scattering effect that occurs as electrons traverse the channel between the source and drain regions of a device. As device geometries continue to shrink, and as the number of devices within a single integrated circuit increases, leakage current can become significant enough to raise the temperature of the semiconductor substrate, thereby slowing the device, and, possibly, raising the temperature of the device above the its operational limit.
The present invention is directed to overcoming, or at least reducing the effects of, some or all of the aforementioned problems.